Chip design becomes more difficult, and its workflow becomes complicated as semiconductor processes evolve. Under this trend, chiplet technology that can simplify chip design and manufacturing workflow, efficiently improve chip performance, and sustains Moore’s Law is highly anticipated in the industry.
From a system design perspective, various hardware functions can be divided into chiplets, which can be manufactured using different IC process nodes and even non-silicon materials to meet the demands for low cost and high performance. According to Omdia’s projections, the global chiplet market size is expected to reach $5.8 billion by 2024 and is projected to exceed $57 billion by 2035.
Chiplet technology involves disaggregating functions originally integrated into SoCs. Challenges such as designing interconnect architectures between multiple chiplets, addressing heat dissipation issues after chip stacking, and managing aspects like chip testing, software integration, and responsibility allocation are common in chiplet endeavors. Addressing these challenges requires corresponding design processes, methodologies, and tool support.
The memory testing and repair IPs introduced by iSTART-TEK, including EZ-Safety, EZ-TEC, and EZ-Monitor, can all be applied in chiplet technology.
EZ-Safety improves memory testing efficiency by extracting essential signals required during memory testing. It automatically backs up designated memory information and is not restricted to testing only in the test mode, thereby enhancing overall security. Additionally, EZ-Safety is easy and intuitive to embed and integrate, providing real-time and flexible memory testing capabilities.
EZ-TEC is also easy to embed and integrate into IP designs. It dynamically adjusts memory testing algorithms, allowing designers to customize element definitions of the testing algorithm according to the specific requirements of individual chiplets, in addition to the commonly used algorithms. EZ-TEC is the world’s first technology to modify memory testing algorithms after chip mass production, thereby improving chip yield.
EZ-Monitor ensures the memory lifecycle within the chip, and effectively monitor the lifecycle of each individual chiplet.
As semiconductor fabrication approaches known physical limits, the continuous enhancement of processor performance necessitates the adoption of chiplet and heterogeneous integration technologies. These approaches are regarded as primary solutions for sustaining Moore’s Law. The memory testing and repair IPs provided by iSTART-TEK are well-suited for chiplet implementations, offering an effective means to improve the yield of individual chiplets.