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EZ-TEC

EZ-TEC

EZ-TEC

EZ-TEC (EZ-TEC SRAM IP)

EZ-TEC can coexist with the existing memory testing circuits of chip design companies. This U. S. patent breaks down memory testing algorithms into elements, allowing users to reconstruct the architecture of any memory testing algorithm through element reorganization.

產品特色

  • Independent of any MBIST EDA tools
  • Reduce DPPM obviously
  • Allow users to change testing algorithms after CP stages

應用

測試介面