EZ-TEC
SRAM Test Solution
EZ-TEC can coexist with the existing memory testing circuits of chip design companies. This U. S. patent breaks down memory testing algorithms into elements, allowing users to reconstruct the architecture of any memory testing algorithm through element reorganization.
Features
- Coexist with existing MBIST’s circuits
- Decouple existing SRAM testing algorithms from Elements
- Element-Based architecture testing algorithms for reducing area obviously
- Easy to change SRAM testing algorithms through JTAG interface, after finishing CP phases
Applications
- Allow users to change testing algorithms after CP stages
Interface
- SRAM Interface
- JTAG
- IEEE1500
- IEEE1149.1
- IEEE1687
- Basic