Memory test and repair leader iSTART-TEK today announced that its self-developed “Memory Test Algorithm Recommendation System” has officially obtained a utility model patent in Taiwan. This system is implemented in iSTART-TEK’s MBIST Algorithm Recommendation Tool (MART), launched in 2026, and leverages AI-assisted automated decision-making to significantly enhance memory test development efficiency.
As semiconductor processes scale down to the nanometer level, memory capacity and complexity within System-on-Chips (SoCs) are growing exponentially, making it a major challenge for designers to identify the optimal algorithm among hundreds or thousands of test options. Traditionally, memory test algorithm selection has relied heavily on the experience of senior engineers. Incorrect choices can not only miss potential defects but also prolong test times and increase production costs. The patented system from iSTART-TEK addresses this long-standing industry inefficiency.
The system first employs a “Question Generation Module” and an “Interface Module” to sequentially generate inquiries and receive corresponding responses, accurately capturing key parameters of memory architecture and application scenarios. Based on these parameters, the “Algorithm Recommendation Module” determines the most suitable test algorithm, while the “Configuration File Generation Module” automatically produces the corresponding configuration information.
Using this tool, engineers can quickly obtain optimized test algorithms and related configuration files, effectively shortening development cycles and improving memory testing efficiency.
iSTART-TEK stated that securing this patent demonstrates the company’s capability not only to provide powerful testing tools but also to help customers make accurate test decisions quickly. Through parameterized guidance, even less-experienced engineers can configure professional-grade memory test solutions in a very short time. The core value of this technology lies in transforming complex test experience into digital logic decisions, optimizing SoC test coverage and production efficiency from the outset.