iSTART-TEK (TW: 6786), the exclusive provider of memory testing and repairing solutions in Asia, has announced that its simplified memory testing development platform, EZ-BIST, has been adopted by China Resources Microelectronics Limited (CR Micro). In their chip development process, EZ-BIST is used as a key tool for the memory test circuit designs, with which the development cycle of memory test circuit can be effectively shortened.
In the upstream supply chain of IC design, iSTART-TEK provides the EDA tool and IP to the IC design companies, design service companies, semiconductor manufacturers, etc. The EDA tools and IPs can help them shorten the IC design development cycle, and enhance the SoC yield rate.
Since the second quarter of 2022, the capacity utilization of many semiconductor foundries has declined, and oversupply has also emerged, leading to excessive chip inventories in many IC design companies. Thus, the IC design companies are wondering about developing new chips. Benefiting from this trend, iSTART-TEK’s performance recovered recently.
Adhering to the original intension of helping developers realize SoC designs in a simpler, faster, and lower-cost way, iSTART-TEK launched EZ-BIST (as shown in Figure 1 below), the world’s first EDA tool that can generates BIST circuits entirely based on the graphic user interface (GUI). Lots of memory test algorithms are built in the GUI (Figure 2) for users to select the most suitable algorithm according to the chip development process and application. In addition, it provides the “fool proofing” feature to prevent errors from manual operations, making the implementation of memory algorithm circuits more easily.
According to iSTART-TEK, the strengths of EZ-BIST are effective reduction of the defect part per million (DPPM), user-friendly operation workflow and numerous types of built-in algorithms.
Driven by multi-functional and high-performance chips, memory defect types that have never appeared in mature processes will occur. How to accurately identify memory defects and reduce DPPM has been highlighted by IC design companies and chip developers. Therefore, it is necessary to adopt professional memory teat tools to reduce DPPM and improve chip quality.
