The behavior of traditional algorithms cannot be modified after chip tape-out, which can lead to defects during usage even if the chip has passed the Chip Probe (CP) test and Final Test (FT). Adding new test algorithms at this stage would significantly increase testing time and costs. Therefore, the flexibility and complexity of algorithms have become critical issues.
iSTART-TEK’s Test Element Change (TEC) system, utilizing a Graphical User Interface (GUI), modularizes algorithm behaviors, allowing them to be rearranged and combined into new algorithms. Even if customers do not adopt iSTART-TEK’s MBIST circuits, they can retain their original BIST architecture and insert EZ-TEC SRAM BIST IP into the existing circuits. This provides significant convenience and flexibility for customer applications. When users encounter issues in SRAM that cannot be detected by the original MBIST circuits, they can use the EZ-TEC SRAM BIST IP to implement new testing algorithms without altering the SRAM architecture. This effectively increases yield rates.
EZ-TEC SRAM BIST IP is a modularized architecture based on iSTART-TEK’s U.S. patent “METHOD FOR GENERATING A MEMORY BUILT-IN SELF-TEST ALGORITHM CIRCUIT.” Each element has its corresponding code, which enables the generation of new algorithms. Users only need to prepare four elements to combine and form a common algorithm like the March C+ algorithm.
Main Strengths of the EZ-TEC SRAM BIST IP
- The EZ-TEC SRAM BIST IP can be independent with any MBIST EDA tools, and coexist with the existing memory testing circuits.
- When the original MBIST circuits cannot detect specific memory defects, new algorithms can be generated through element reorganization for re-testing, effectively reducing DPPM (Defective Parts Per Million).
- The Building-Block architecture enables the construction of the most cost-effective circuits.
- Reorganize new algorithms to test critical memories, ensuring comprehensive memory test coverage.
- Easily select memory test algorithm elements, increasing the flexibility and reliability of chip design.
iSTART-TEK’s EZ-TEC SRAM BIST IP offers flexible reconfiguration of test algorithms. During the CP/FT stages, test engineers can modify the testing patterns on the machine, thereby enhancing memory test robustness, providing users with significant convenience and flexibility.
News: https://www.moneyweekly.com.tw/ArticleData/Info/Article/156140