This innovative tool flow is specifically designed to analyze memory testing results and reduce memory testing file transfer time. With this technology, all memory testing results within the SoC can be efficiently analyzed. Complemented by iSTART-TEK’s suite of EDA tools, including STIL patterns, meminfo (for recording memory testing data and algorithms), testbench (which facilitates circuit simulation and testing export data), and the testing results generated by an ATE, the “Configurable ATE Tool Flow” enables comprehensive testing of all memories within an SoC and analysis of memory error information. This delivers enhanced convenience and efficiency in memory testing services for customers.
