As the semiconductor processes is getting sophisticated, the demand for SRAM keeps increasing. The reason is that chips such as high-performance computing (HPC) and microcontrollers (MCU) chips require an SRAM to store the major program that drives the chip to run. To accurately control the chip yield, how to accurately identify SRAM defects during CP testing and reduce the defect parts per million (DPPM) has become a major issue for IC design companies and chip developers. Therefore, it is very critical to ensure the reading and writing of the SRAM is properly working when the chip is powered on.
STARTTM v3 and EZ-BIST developed by iSTART-TEK provide the Power-On Test (POT) feature, which allows for immediate memory testing after the chip is powered on. It helps to validate the correctness of the reading and writing of the SRAM. These tools can also be used in conjunction with the user-defined memory testing algorithm development platform, UDA (User Defined Algorithm), to execute simplified or customized memory testing algorithms after the chip is powered on.
After the testing process when the chip is powered on, the POT feature not only detects the defective memories, but also repairs the defective SRAM, thereby extending the chips’ lifetime.
To meet the chips’ strict requirements for power-on testing time, iSTART-TEK provides the Reduced Test feature, which enables the chip to immediately execute the “March C+” testing algorithm after power-on, completing the memory testing process in a very short time.
With the tools mentioned above, iSTART-TEK can fully meet the strict requirements of memory reading and writing accuracy for chips in high-performance computing (HPC) chips, automotive electronics, and USB Type-C chips.