As automotive electronics, AI computing, and high-performance computing (HPC) continue to advance, the amount of embedded SRAM in modern SoCs is growing rapidly. In many advanced-node designs, SRAM already occupies more than 50% of total chip area. At the same time, process scaling has introduced increasingly complex memory defect mechanisms, ranging from traditional Stuck-at Faults and Transition Faults to Read Disturb, Coupling Faults, and Retention-related issues. These challenges place greater demands on test coverage, product reliability, and DPPM control.
Conventional EDA memory test solutions typically rely on fixed algorithm libraries, making it difficult to address the diverse requirements of different process technologies, application scenarios, and quality targets. Excessive testing can significantly increase test time and cost, while insufficient testing may lead to yield loss and product quality risks. As a result, memory test strategies are evolving from standardized methodologies toward more flexible and application-driven approaches.
To address these challenges, iSTART-TEK developed UDA (User-Defined Algorithm) and TEC (Testing Elements Change), transforming memory testing from fixed algorithms into modular and reconfigurable test elements. Engineers can freely assemble and optimize test strategies according to process characteristics, application requirements, and DPPM objectives. Whether the goal is to improve defect coverage, optimize test efficiency, reduce power consumption, or achieve stricter quality targets, UDA/TEC provides a highly flexible testing framework.
UDA is further certified to the ISO 26262 TCL1 standard, supporting the stringent functional safety and reliability requirements of automotive applications. Through modular test architecture and user-defined algorithm capabilities, iSTART-TEK helps customers achieve the optimal balance between quality, cost, and efficiency, while enabling differentiated memory test strategies for next-generation SoC products.