EZ-TEC IP: Componentizing Algorithms to Enhance Testing Efficiency
EZ-TEC (Easy Test Element Change IP) can modularize testing algorithms into components. With flexible combinations of these components, users can create brand new testing algorithms capable of detecting SRAM memory defects in advanced processes. After chip production, users can still adjust algorithm behaviors at the CP stage to improve chip yield and reduce DPPM (Defective Parts Per Million).
Whether maintaining the original BIST architecture or adopting other vendors’ MBIST solutions, EZ-TEC IP can reconfigure new testing algorithms specifically for important or large-area SRAM.
EZ-TEC IP Workflow
Let’s take a look at the EZ-TEC IP architecture. SRAM_s represents the original SRAM interface, and SRAM_t the interface that connects SRAM after MBIST processing. Users can add circuits with IP and retain the original architecture.
Next, the figure shows the interfaces corresponding to different types of SRAM.
Uses can utilize an external interface (e. g. JTAG) and send_command in the testbench to set and modify testing algorithm behaviors:
ALG_CMD is composed of direction, cmd_parity, and action, as shown in the following example:
Every component has its corresponding code. Users can reconfigure new algorithms through these code combinations, as shown in the new algorithm behavior on the screen.
The Reason Why You Need EZ-TEC
When users encounter SRAM issues that the original MBIST circuitry cannot detect, they can utilize the EZ-TEC SRAM IP to add new testing algorithms, thereby improving the chip yield. Additionally, EZ-TEC has no process limitations and supports all advanced processes, making it a crucial tool for enhancing chip testing efficiency.