In the previous episode, we introduced the memory test and repair-related EDA tools, START and EZ-BIST, provided by iSTART-TEK. Today, we have invited Tina, a senior software engineer at iSTART TEK, to introduce the solutions for automotive electronics and HPC applications.
In the last episode, we mentioned the EDA tools provided by iSTART-TEK, offering advanced features for automotive electronics and HPC chips. What features are provided specifically for these applications?
For automotive electronics chips, we offer features such as Power-On Test, Error-Correcting Code, and Testing Elements Change. POT can be implemented in different ways, including recording the test process in ROM to control the test commands, using RTL or a signal to control, and implementing it through the CPU. If using the CPU, it enables “Memory Status Watch-Dog,” allowing immediate memory testing and repair after powering on the chip. It ensures repaired memory operates correctly by testing it immediately. Additionally, POT includes “BIST Circuit Self-Verification,” which involves self-checking the accuracy of the memory test circuit through the Error Injection mechanism. ECC is used to ensure data correctness during the runtime of the system, and TEC optimizes memory test algorithms by flexibly adjusting memory test units. These features focus on enhancing and ensuring security, meeting safety requirements for automotive electronics application.
What about customized solutions for HPC chips? What features are provided?
In addition to providing POT, we offer Multi-Chain, Power Consumption Analysis Mechanism, and Memory Group Based on Layout Definition File for HPC application. Multi-Chain allows users to plan any number of chains based on SoC design requirements, controlling power consumption and transmission speed through multiple repair chain functions for diverse SoC designs. PCA manages the power consumption of memory groups based on memory power consumption information. When the total power consumption of grouped memory exceeds the SoC’s power limit, it automatically reorganizes memory groups. MGD allows users to create a memory grouping mechanism based on existing layouts. These features, along with previously introduced POT and TEC, are solutions customized for HPC chips.