iSTART-TEK held a product launch in Shanghai on March 25, introducing START™ v5 and EZ-BIST™ v2. START™ v5 is an EDA tool for SRAM testing and repair, while EZ-BIST™ v2 is an EDA tool specifically for SRAM testing. In terms of performance improvements, both START™ v5 and EZ-BIST™ v2 leverage AI tools, including ChatGPT, OpenAI, and DeepSeek, to enhance RTL syntax coverage and support for various commands. Compared to START™ v3, these enhancements boost execution efficiency by 50%. Additionally, START™ v5 and EZ-BIST™ v2 significantly improve the efficiency of identifying various types of SRAM, reducing SRAM identification time by 50% compared to START™ v3.
Furthermore, START™ v5 and EZ-BIST™ v2 have enhanced the Auto-Clock Tracing function for SRAM, allowing MCU-based chips to automatically identify SRAM clock paths within the chip, thereby improving the speed of SRAM circuit testing for MCU-based chips.
iSTART-TEK’s START™ v5 has obtained ISO 26262 TCL1 certification, with several features meeting the requirements for automotive electronic chips. The latest enhancements include the addition of a dynamic control interface for SRAM in the POT (Power-On Test) function. Instead of storing POT control commands in ROM, they are now stored in SRAM, allowing for dynamic adjustments to the POT control commands.
Enhancements in START™ v5’s SRAM repair technology include:
1. Reduced latency in transferring SRAM error information from eFuse or OTP to the SRAM repair controller during the repair process.
2. Introduced data compression for eFuse and OTP required in SRAM repair, addressing the increasing complexity of AI chip designs and the growing demand for SRAM. This significantly reduces AI chip costs.
3. Optimized the timing of SRAM repair paths to accommodate the increasing SRAM demand in AI chips, enhancing overall flexibility in chip placement and routing.
4. Enhanced the patented SRAM repair technology by strengthening the coexistence mechanism of Stand-Alone SRAM and Redundancy. This improvement gave consumer electronic chip designs more flexibility, allowing unused SRAM space to be fully utilized as backup memory for repair, significantly reducing design costs for consumer chips.
5. Strengthened the modular (Bottom-Up) design workflow to support the Chiplet architecture, simplifying the generation of SRAM testing and repair circuits for complex chips. Additionally, ensured compliance with SRAM testing standards under the Chiplet architecture.
In terms of SRAM error diagnosis, START™ v5 and EZ-BIST™ v2 have enhanced SRAM error analysis capabilities, allowing the diagnostic function to work in conjunction with the chip’s layout diagram. This enables precise identification of SRAM error locations within the chip and their root causes.
START™ v5 and EZ-BIST™ v2 have also strengthened the SRAM clustering mechanism, which can be integrated with the chip’s layout diagram to ensure proper timing requirements for placement and routing.
For SRAM testing algorithms, START™ v5 and EZ-BIST™ v2 feature TEC 2.0 (Testing Element Change) that is designed based on iSTART-TEK’s patented UDA (User Defined Algorithms) architecture. TEC enables dynamic modification of SRAM test algorithms during the CP (Chip Probing) stage simply by changing tester commands, without requiring any modifications to the chip design. This makes DPPM (Defective Parts Per Million) control much more manageable.
The key advantage of TEC lies in the UDA patent, which allows modularization of SRAM testing algorithms—similar to stacking LEGO bricks. By recombining these modular components, new SRAM test algorithms can be generated. This enables chip developers to design customized SRAM test algorithms based on specific chip functions and applications, ultimately reducing DPPM rates.
iSTART-TEK’s new products, START™ v5 and EZ-BIST™ v2, provide solutions for AI chips and automotive electronic chips, enhancing chip yield rates, reducing testing costs, and increasing market competitiveness.
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