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iSTART-TEK to Launch a Comprehensive DFT Solution to Enhance Testability and Mass Production Quality of Advanced Chips

By March 4, 2026No Comments

As IC design complexity continues to escalate, a single chip now integrates hundreds of millions or even billions of transistors. Traditional post-manufacturing test methodologies are no longer sufficient to effectively cover all potential fault modes. To ensure high yield and reliability in mass production, Design for Testability (DFT) has become a critical component of the modern VLSI design flow.

Beginning in the second quarter of 2026, iSTART-TEK plans to introduce a comprehensive DFT EDA solution in collaboration with strategic partners. This solution will provide customers with a complete DFT implementation and verification platform from RTL through the pre-tape-out stage, enabling design teams to establish a robust testability architecture at the early stages of a project. By integrating DFT early in the design cycle, customers can shorten development timelines and improve overall design quality.

DFT comprises a series of techniques embedded during the design phase to enhance the observability and controllability of internal chip nodes, thereby improving post-fabrication test efficiency and fault coverage. A complete DFT architecture enables effective detection of common fault models, including Stuck-At Faults, Transition Faults, Path Delay Faults, Bridging Faults, and Open / Stuck-Open Faults. In industry practice, Stuck-At Fault coverage typically exceeds 99%, while Transition Fault coverage is generally required to surpass 95% to meet high-quality mass production standards.

iSTART-TEK’s DFT technology is built upon its strong foundation in memory testing, particularly Memory Built-In Self-Test (MBIST). Memory testing has become an indispensable element of modern SoC design. As embedded SRAM and other memory capacities continue to increase, memory blocks frequently represent the primary source of yield and reliability risks. With extensive expertise in MBIST architecture and test algorithm development, iSTART-TEK delivers high-coverage and high-efficiency testing solutions tailored to different memory types and process characteristics, helping customers effectively mitigate potential failure risks prior to volume production.