Skip to main content
iStart ClassMultimedia LibraryNews&Events

Episode 36: SRAM Testing Algorithm for Automotive-Grade Chips Part 3: Using UDA + TEC to Generate a Full-Coverage SRAM Defect Testing Algorithm

By June 30, 2025July 1st, 2025No Comments

With the continuous adoption of advanced semiconductor processes like FinFET and GAA, while chip performance improves, the defect types of SRAM have also become more complex. New types of faults, such as Marginal Faults, Dynamic Faults, and even Soft Errors, are emerging—similar to how viruses mutate. Traditional March C testing algorithms are like “old vaccines”: they may still be effective against some known defects, but they fall short when it comes to these “virus mutations.”

To tackle this challenge, iSTART-TEK offers the UDA (User-Defined Algorithm) mechanism. Simply put, it works like a vaccine development platform, allowing customized testing algorithms to be tailored according to the characteristics and usage scenarios of the product. For example, if a product needs to operate in high-temperature environments, where leakage defects are more likely to occur, users can design algorithms with specific test patterns targeting such defects. It’s like administering targeted vaccines to high-risk areas for enhanced protection.

In summary, the combination of UDA and TEC forms a tailor-made, comprehensive vaccine program for SRAM. As processes and application requirements continue to evolve, only by continuously updating testing algorithms can we guard against emerging defects, ensuring reliability and quality in critical fields such as automotive, AI, and aerospace.