In automotive applications, SRAM plays a critical role as temporary storage and high-speed buffering. However, it is also exposed to extreme temperature and voltage conditions, making it prone to various potential failures. For automotive-grade chips that need to meet ISO 26262 ASIL-C or ASIL-D requirements, any memory defect could pose a functional safety risk to the system. Therefore, it is crucial to understand and cover all potential SRAM failure types.
These failures can generally be categorized into three groups based on operational behaviors: write operations, read operations, and combined write-read operations.
Failures Related to Write Operations
- Stuck-At Fault (SAF): The memory cell cannot be written as 0 or 1, often due to damage in pull-up or pull-down transistors.
- Write Disturb Fault (WDF): Writing to one cell accidentally flips the value of a neighboring cell.
- Access Fault & Open Fault: Abnormal conduction in wordlines or bitlines prevents signals from being properly written.
Failures Related to Read Operations
- Stuck-At Fault: Similar to write SAF, but caused by errors in sensing circuits, making the read value consistently incorrect.
- Read Disturb Fault (RDF): The act of reading unexpectedly alters the data in the cell, especially in cells with weak data retention.
- Deceptive Read Destructive Fault (DRDF): The read appears successful, but it has silently corrupted the actual cell content.
- Data Retention Fault (DRF): Data disappears over time, often related to leakage or weak latch strength.
Failures Triggered by Combined Write-Read Operations
- Transition Fault (TF): The cell cannot switch from 0 to 1, or from 1 to 0. Alternating write and read operations are required to detect it.
- Dynamic Faults: Failures that only occur after sequences like two writes followed by two reads. Detection requires algorithms like March C- or March SS.
For automotive SoCs, considering their demanding environmental and reliability requirements, all of the above failure types are considered high-risk and must be thoroughly covered. Failures such as WDF, RDF, TF, and DRF become even more severe under high-temperature/high-voltage or low-temperature/low-voltage conditions, making customized test algorithms essential for targeted coverage.
So, how should we address these errors? The answer is to design SRAM testing algorithms tailored to these failure types. By leveraging iSTART-TEK’s UDA (User Defined Algorithm) and TEC (Test Element Change) technologies, high-coverage, flexible test sequences can be generated to not only enhance the quality of automotive chips but also meet the functional safety requirements of ASIL-C/D.