As one of the most prominent point tool providers in the EDA industry, iSTART-TEK has recently launched START™ v5, a cutting-edge development environment for memory testing and repair circuits. This release showcases the core strengths of a point tool—precision and a relentless pursuit of perfection.
START™ v5 offers the following advantages typical of a point tool:
- RTL syntax identification efficiency improved by 50%.
- SRAM BIST circuit generation speed increased by 50%.
START™ v5 is highly focused on enhancing SRAM repair technology, with several newly introduced and reinforced features:
- Reduced the latency in transferring SRAM error data from eFuse or OTP to the repair controller during the repair process.
- Enhanced data compression for eFuse and OTP, optimizing storage and access during SRAM repair.
- Optimized repair path timing, improving the flexibility of overall chip layout and routing.
- Strengthened the SRAM repair mechanism supporting the coexistence of standalone and redundancy modes.
- Improved the bottom-up design flow, simplifying the generation of SRAM test and repair circuits for complex chips.
START™ v5 also introduces and enhances a range of features for SRAM fault diagnosis and analysis:
- By utilizing the chip’s layout diagram, it can accurately identify the faulty SRAM locations within the chip and pinpoint the root cause of the failure.
Fully leveraging the strengths of a point tool, START™ v5 introduces a patented UDA (User Defined Algorithm) architecture for SRAM test algorithms. Built on this foundation is the world’s first and exclusive TEC (Testing Element Change) technology.
Key features of TEC include:
- Modular decomposition of SRAM test algorithms, similar to assembling LEGO bricks, where each test component is implemented as a modular hardware block. This approach significantly reduces the circuit area required for implementing test algorithms.
- At the CP (Chip Probing) stage, users can dynamically modify SRAM test algorithms simply by reordering test commands through ATE (Automated Test Equipment), without changing the chip design. This allows highly flexible control of DPPM (Defective Parts Per Million).
Although START™ v5 is a point tool, it is fully compatible with third-party EDA tools, enabling seamless integration within DFT flows.
Moreover, START™ v5 is the first memory test and repair development environment in the world that supports the generation of BIST circuits for CIM (Computing in Memory) architectures.