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Highly configurable RRAM IP testing and repairing circuits development environment: EZ-NBIST

By November 15, 2023No Comments
  1. Testing methodologies of RRAM IP

The testing methodologies of RRAM IP covers full wafer sort, and final test for UMC’s 22nm process and customized embedded RRAM IP.

iSTART-TEK develops EZ-NBIST GUI tool to save BIST coding time of RRAM IP.

EZ-NBIST follows RRAM vendor’s testing methodologies to implement all test items’ timing diagrams and save parallel long testing time in ATE.


  1. Why RRAM IP needs to use BIST and BISR?

RRAM IP has complicated testing functions to cover each disturbing condition in 22nm process.

The memory BIST adds logic to an IC which allows the SoC to test its own memory operation.

MBIST tests the RRAM macro through an effective test algorithm to detect possibly all the faults. MBIST generates test patterns from RRAM vendor requirement to the RRAM macro and reads them to find any RRAM defects.

BISR adds repair circuit to backup memory to increase the RRAM IC yield.


  1. How iSTART-TEK accomplish BIST and BISR of RRAM IP?

iSTART-TEK develops EZ-NBIST GUI tool to generate BIST and BISR of RRAM IP.

iSTART-TEK BIST implements all RRAM test items to cover wafer soft and final test. BIST interface is a flexible serial interface to reduce IC test pins. Increase BIST test flexibility, all test items can be enabled and disabled individually. Provide diagnosis mode to debug defect address.

iSTART-TEK BISR records RRAM faulty memory address and use redundancy to increase RRAM IC yield. Provide auto repair function.