As AI home appliances, smart displays, and voice-controlled devices become increasingly widespread, chip architecture is shifting from a compute-centric approach to one focused on memory efficiency. With AI inference moving from the cloud to the device (Edge AI), data movement has become a major source of latency and power consumption, making memory a critical factor in system performance.
Under this trend, AI chips are evolving from a “separated compute and memory” model toward Computing-in-Memory (CIM), where SRAM not only stores data but also directly participates in computation. While this significantly reduces data movement and improves efficiency, even minor memory defects—such as soft errors or timing instability—can directly impact AI inference accuracy. As a result, testing requirements are moving beyond basic functional verification toward ensuring stability and accuracy under high-frequency, high-load conditions.
To address these challenges, iSTART-TEK provides UDA (User-Defined Algorithm) and TEC (Test Element Control) technologies, enabling flexible test architectures and high-coverage detection. These solutions help identify subtle memory defects in CIM-based designs, reduce DPPM, improve yield, and ensure reliable performance of AI chips in mass production and real-world applications.