Recent news of NVIDIA’s acquisition of Groq has sparked widespread discussion, putting AI-specific processors such as TPU, LPU, and NPU back into the spotlight. Whether in cloud data centers, edge AI, or automotive and industrial applications, computing architectures are rapidly shifting from general-purpose CPUs to accelerators tailored for specific workloads. Yet behind these differently named and positioned processors lies a common and critical core: SRAM.
The Common Foundation of TPU, LPU, and NPU
Although TPU, LPU, and NPU have different design goals, they all focus on high throughput, low latency, and energy efficiency. In practice, large volumes of weight data, feature maps, and intermediate results must be repeatedly and rapidly accessed. Compared with DRAM, SRAM offers low latency, high bandwidth, and predictable timing, making it an indispensable memory component in these AI accelerators.
In TPUs, SRAM is often used as large on-chip buffers to support data reuse in matrix operations; in LPUs, which emphasize low-latency inference, SRAM is critical for real-time responsiveness; and in various NPU designs, SRAM capacity, access parallelism, and reliability often directly impact overall AI performance and power efficiency.
From “Memory-Assisted Computing” to “Computing-in-Memory”
As AI models continue to scale, the energy consumed by moving data between compute units and memory has become a major bottleneck for performance and power. This is precisely why Computing-in-Memory (CIM) architectures have attracted significant attention. The core idea of CIM is to perform part of the computation directly within the memory array, drastically reducing data movement and overcoming the limitations of the traditional von Neumann architecture.
For TPUs, LPUs, and NPUs that already heavily rely on SRAM, incorporating SRAM-based CIM in specific computational scenarios is widely regarded as a necessary evolutionary step. By integrating computing capabilities within or around the SRAM, AI accelerators can significantly improve energy efficiency while maintaining high reliability, making CIM a key technology for next-generation AI chips.
CIM Goes Beyond Performance: Reliability and Security Matter
The design challenges of CIM go beyond mere performance. Memory variability, aging effects, and the added complexity of coupled compute-and-store operations all make SRAM testing and repair more critical than ever. In high-reliability applications such as automotive and critical infrastructure, CIM cannot be truly mass-produced and deployed without comprehensive test and repair mechanisms.
Meanwhile, post-quantum security requirements increasingly demand the integration of AI with cryptographic computation. The ability to execute next-generation cryptographic algorithms efficiently under low-power conditions has become a critical requirement for smart devices and automotive systems.
Essential Memory Technologies for the AI Computing Trend
In this context, SRAM quality—critical for the performance and cost of TPU, LPU, and NPU—as well as CIM architectures, is increasingly recognized as a crucial path to overcoming data-movement bottlenecks. iSTART-TEK’s long-standing expertise in SRAM testing and repair, coupled with its CIM architecture development, positions the company as a key driver of technological advancement.
iSTART-TEK is dedicated to providing specialized EDA tools and IP for testing and repairing various types of memory, offering authorized customers a one-stop design. In recent years, iSTART-TEK has also actively invested in CIM architecture R&D, redefining energy efficiency limits for AI computing. The SRAM-based CIM architecture currently under development supports 8-bit compute precision with ultra-low power consumption and offers strong scalability, with further compatibility for RRAM-based designs to meet diverse application needs.
Facing the security challenges of the quantum era, iSTART-TEK has pioneered the integration of lattice-based cryptography and NTT computation optimization techniques, accelerating post-quantum cryptographic algorithms via the CIM architecture to provide long-term, robust security for smart devices and automotive systems. Beyond CIM architecture development itself, iSTART-TEK also provides a CIM test circuit development environment, ensuring that advanced memory computing technologies not only compute fast, but also test accurately and operate reliably. Amid the ongoing evolution of TPU, LPU, and NPU architectures, iSTART-TEK’s deep SRAM expertise has become a critical force in driving CIM and AI chips toward higher efficiency, reliability, and energy savings.