芯測科技股份有限公司

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2020-09-23
iSTART cooperates with Peking University to provide an online course of memory testing and repairing
iSTART-TEK (iSTART, TW-6786) cooperates with school of electronics engineering and computer science Peking University to provide an online course of memory testing and repairing. Among the many applicants, Peking University carefully selected undergraduate, master, and doctoral students from famous universities - including Peking University, Shandong University, Jilin University, University of Nottingham Ningbo China, North China Electric Power University, Beijing Institute of Technology, and University of Science and Technology of China – to participate in this course. In addition to the technical description, the content of the course also combines practical applications, and the course can be replayed after class for reviewing.
 

According to statistics from the United Nations, 1.5 billion students worldwide have been affected by the pandemic, and schools in 185 countries or regions have been closed or partially closed. Before the outbreak of the pandemic, iSTART has been holding online technical seminars and publishing technical white papers to provide information on various innovative technologies to relevant practitioners and research units of DFT testability design constantly. Moreover, under the influence of the pandemic, online courses will be an effective way to maintain teaching, and will not be restricted by time and space. The summer online course in cooperation with Peking University is a part of the plan of iSTART’s university program. It hopes that the online course will reduce the impact of the pandemic on student learning and at the same time bring practical needs into the schools’ teaching curriculums.


Furthermore, the atmosphere of the course was heat up, meaning that students were very active to ask questions. The success of the course has also made us more aware of the relevant needs of the college. In the future, iSTART will take this cooperation with Peking University as an opportunity and continue to launch relevant courses and cooperate with Electronic Engineering departments, Electrical Engineering departments, Computer Science and Information Engineering departments, and other departments related to information to continuously optimize university programs and the mode of education and training assists in training relevant talents in the field of DFT testability design.


As the development of 5G, Artificial Intelligence (AI), and new-generation SoCs, integrated circuits are moving to a more advanced technology node. SoCs reduce test cycle and cost of chips via testability design including built-in memory testing and repairing. In mass production, the control of product quality (Defective Parts Per Million, DPPM) has become more and more important, leading related design requirements to increase. iSTART observed the trend to set up testability design departments through experience of visiting customers but suffer from the lack of relevant human resources. Consequently, iSTART aims to help customers to train talents in DFT testability design through university program by corporations with Electronic Engineering departments, Electrical Engineering departments, Computer Science and Information Engineering departments, and other departments related to information.
 

iSTART provides total solutions for various memories, including SRAM, DRAM, eFlash, MRAM/RRAM, and MTP. The EZ-BIST, a simplified memory testing development platform, is an EDA tool that provides developers a more automated and faster way while designing multi-functional memory testing and repairing circuits. With high performance, low power consumption, and programmable and pipeline structural memory testing technology, EZ-BIST features programmable algorithm, bottom-up circuit insertion, hardware sharing architecture, diagnosis, power-on self-test, and dynamic memory testing. It allows users to easily build optimized memory testing and repairing circuits, greatly reduces design and testing cost and increase the yield rate of chips, in the end, improves product competitiveness.