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Reduce Memory Testing Cost & Increase Chip Yield Rate
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START (SoCs' Built-in Testing And Repairing Technology)
STARTTM v2 (SoC's memory Testing And Repairing Technology) is a complete memory testing and repairing solution for generating BIST and BISR circuit and inserting them into customer's design automatically. STARTTM v2 's friendly interface and menu style constructive configuration assists users to fulfill DFT for all kind of IC design simply.
Features
- Support Stand-alone repairing technical for memories without redundancy
- Support UDM (User Defined Memory)
- Support memory grouping setting
- Support auto clock tracing
- Support gate-cell insertion for power saving
- Support POT (Power-On Testing)
- Support DMT (Dynamic Memory Testing)
- Support advanced testing algorithms for MRAM & ReRAM
- Smart fool-proof design
- No Memory instance limitation
- GUI interface
- Advanced repairing architecture
- Multi-chain design
- Bottom-up flow
- Programmable algorithm
- Multiple memory testing algorithms
Application
- Automotive
- SSD
- Security
- AI
- Edge Computing
- Network
- High Resolution TCON
- AIoT
Testing Interface
- JTAG
- IEEE 1149.7
- IEEE 1687
