芯測科技股份有限公司

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2020-12-21
iSTART cooperates with National Central University

iSTART-TEK (iSTART, TW-6786) announced cooperation with National Central University to provide memory testing Electronic Design Automation (EDA) tools and relative courses. It assists students in relative departments in National Central University to cultivate memory testability design concepts and professional capability via using the most advanced memory testing tools, which gears themselves to memory testing industry and improve their competitiveness in future employment.

 
The advantages of memory testing circuit developing EDA tools include a fully graphical user interface (GUI), easy operation, short learning curve, and foolproof design to avoid human errors. MBIST circuit design can be automatically completed through step-by-step simple interface after pressing the execute button.
 

As the development of 5G, Artificial Intelligence (AI), and new-generation SoCs, integrated circuits are moving to a more advanced technology node. It has become more and more important to reduce SoCs testing cycle and cost via testability design including built-in memory testing and repairing, and to control product quality (Defective Parts Per Million, DPPM) in mass production, leading related design requirements to increase. iSTART observed the trend to set up testability design departments during customers visit but suffer from the lack of relevant human resources. Consequently, iSTART aims to help customers to train talents through university program which cooperates with Electronic Engineering departments, Electrical Engineering departments, Computer Science and Information Engineering departments, and other departments related to information. At present, it has successfully cooperated with well-known universities, including Peking University, Nanjing University of Posts and Telecommunications, Chung Hua University, and National Central University to help take root in testability design technology.

 
iSTART announced “the forward-looking and reliable system laboratory of Electrical Engineering department, National Central University is devoted to memory testing and repairing, AI circuit design and testability design, and three-dimensional integrated circuit design and testing. Its research results are obvious to all. iSTART hopes to contribute relevant research of the laboratory through donating its memory testing EDA tools in this cooperation. At the same time, iSTART plans to discuss further industry-academic collaborations with National Central University and hopes the relevant substantive cooperation can execute as soon as possible in the foreseeable future.”
 

Dr. Jin-Fu Li of Electrical Engineering department, National Central University indicated that this cooperation with iSTART is just a beginning. In the future, we will develop in-depth industry-academic research cooperation in innovation, research, and education to improve students’ technological practices, expand their scientific research experience, and enhance their integrated circuit design capabilities. 

 
iSTART, a leading developer in memory testing and repairing technology, provides total solutions for various memories, including SRAM, DRAM, eFlash, MRAM/RRAM, and MTP. EZ-BIST, a simplified memory testing development platform, is an EDA tool that aims to help developers with a simpler, faster, and lower-cost way to optimize memory testing circuits. With high performance, low power consumption, and programmable and pipeline structural memory testing technology, EZ-BIST sets relevant parameters and options via easy-to-use graphical user interface (GUI), automatically identifies and groups the memory of the SoCs, and features testing algorithm, hardware sharing architecture, diagnosis dynamic memory testing, and automatic integration of design circuits. It allows users to easily build optimized memory testing and repairing circuits, greatly reduces design and testing cost and increase the yield rate of chips, in the end, improves product competitiveness.