With the surge of AI, computing at the edge, IoT, and the resulting chip demand raised. The driver chip run thru SRAM, where the executing program was installed.Target to reduce the memory testing cost, precisely detect the SRAM failure is highly important. Afterwards, choosing the economic and efficient testing tool and memory test algorithm is always addressed by the chip manufacture.
iSTART-TEK focuses on innovation of memory testing and repairing technology, providing SoC designers with reliable memory testing and repairing solutions. In addition, the solution offers customization represents a pioneering approach in chip development process.
We are introducing iSTART-TEK latest “User Defined Testing Algorithms” architecture, which enable user to define the memory testing with user manual, and benefit by optimizing memory testing with cost down.A promising solution integrates GUI to iSTART-TEK’s existing “User Defined Testing Algorithms” architecture and allow user easily define flexible memory testing Algorithms.Chip maker is enabled to uniquely define the customized Testing Algorithms by “User Defined Testing Algorithms” architecture.Simultaneously, you can expect greatly reduces the memory testing cost by decreasing DPPM.
iSTART-TEK’s “User Defined Testing Algorithms” was created to respond to chip maker set to hike price. It allows user to define testing algorithms which minimize DPPM with corresponding SRAM in SoC, chip manufacture process and final product application. An unexpected increase in demand for memory, triggered by chip maker’s raise price and higher chip design complexity. An efficient Algorithms is essential to IC design house.
iSTART-TEK’s “User Defined Testing Algorithms”was aimed to detect the SRAM failure and achieve high-confidence testing cost.Addressing the fault SRAM in SoC is key to significantly decrease chip development cost and ensure effectively decrease DPPM. iSTART-TEK plays a vital role in the chip development and has a vibrant and flourishing future.