With the surge of AI, edge-computing, IoT, the demand for chips has increased.. These chips utilize SRAM as the main storage for the program that drives the chip’s operation. To reduce the memory testing cost, it is important to precisely detect the SRAM failures. Thus, choosing a memory testing algorithm that balances precision and cost-effectiveness is always a concern for chip manufacturers.
iSTART-TEK specializes in the innovation of memory testing and repairing technology, providing SoC designers with reliable memory testing and repairing solutions. The company also offers customized design services that plays a crucial role in chip development process.
iSTART-TEK has introduced its latest “User Defined Testing Algorithms” architecture, which enables chip manufacturers to easily define memory testing algorithms with the user manual, thereby improving memory testing accuracy and reducing costs. The “User Defined Testing Algorithms” architecture is integrated with GUI, allowing chip manufacturers to define customized testing algorithms with higher flexibility. Not only the cost but also DPPM can be greatly decreased through the use of this new architecture.
iSTART-TEK’s “User Defined Testing Algorithms” was introduced to address the increasing cost concerns of chip manufacturers. It allows users to specify the most suitable testing algorithms for their f SRAM in SoCs, chip manufacturing process and final product applications, while minimizing DPPM.
Wafer foundries’ price rise and high complexity of chip design have resulted in a surge of demands for memories. Thus, IC design companies require high-efficient and cost-effective memory testing algorithms. iSTART-TEK’s “User Defined Testing Algorithms” can help detect the SRAM failures and further reduce chip testing costs. Addressing the failed SRAM in SoCs is critical to effectively decrease chip development cost and DPPM. iSTART-TEK’s core technology makes it essential in the entire chip development process and has a promising future ahead.